The present invention is related in general to integrated circuits (ICs), and more particularly to an apparatus and method for bit line sensing in memory devices.
A static random access memory (SRAM) is a well-known memory device that is capable of storing millions of bits of information. Unlike the dynamic random access memory (DRAM) which requires a periodic refresh, the SRAM memory typically does not require a periodic refresh, thereby making it faster. The bits of information are stored in individual memory cells organized as an array of rows and columns to make efficient use of space on a semiconductor substrate used in the fabrication of the SRAM.
A well-known architecture in the design of a memory cell uses six metal oxide semiconductor (MOS) transistors, e.g., a 6T memory cell. Four transistors defining an SRAM cell core are configured as cross-coupled inverters, which act as a bistable circuit, retaining the state imposed onto it while being powered. Each inverter includes a load transistor and a driver transistor. The output of the two inverters is complementary to one another, except during transitions from one state to another. Two additional transistors known as “pass” or “access” transistors provide access to the cross-coupled inverters during a read operation (simply referred to as read) or write operation (simply referred to as write). The gate inputs of the pass transistors are typically connected in common to a “word line”, or WL. The drain of one pass transistor is connected to a “bit line”, or BL, while the drain of the other pass transistor is connected to the logical complement of the bit line, bit line bar, BLB, or BL_.
The 6T memory cell may be vulnerable to stability problems since the read and the write operation share some of the devices. Trend towards lower operating voltages and adoption of deep submicron technologies (e.g., below 65 nanometers) may exacerbate the problems. The stability problems often arise when stored charges on the internal storage nodes of the cell core are disturbed. In standard 6T memory cells, this may arise, for example, during a read operation in which an access transistor is connected to an internal node having a stored logical “0” (e.g., ground potential) associated therewith is activated with a logical “1” (e.g., high logic value) being present on the corresponding bit line. In this instance, the internal node is pulled above ground potential through the corresponding access transistor, which may unintentionally flip the logical state stored in the 6T memory cell. The stability of the 6T memory cell may be improved by adding two transistors, which generally results in an increase in the silicon area. An 8 transistor (8T) memory cell generally provides separate mechanisms to read data from the cell and write data to the cell, thereby enabling optimized performance and optimized sizing for the separate (or decoupled) read and write operations.
FIG. 1 illustrates an architecture of a traditional 8 transistor (8T) memory cell 100, according to prior art. In the depicted embodiment, a read circuit 102 for the 8T memory cell 100 includes a read access transistor 110, a read pull-down transistor 120 (also referred to as a read drive transistor), and a read bit line bar (RBLB) 130. A word line WL 104 is coupled to the gate of the read access transistor 110, thereby controlling its operation. The core cell 150 includes a first node T 152 to store a bit value, with a second node C 154 storing a complementary value relative to the first node T 152. The first node T 152 is coupled to the gate of the read pull-down transistor 120, thereby controlling its operation. A drain of the read pull-down transistor 120 is coupled to a source of the read access transistor 110, a source of the read pull-down transistor 120 is coupled to a ground level bias supply Vssm 160, e.g., 0.3 volts, and a drain of the read access transistor 110 is coupled to the RBLB 130.
The RBLB 130 is precharged to a logic high, e.g., 1.1 volts prior to the read operation. When a bit value stored at the first node T 152 is a logic high and when the word line WL 104 is asserted to a logic high, the read access transistor 110 and the read pull-down transistor 120 provide a low resistance path between RBLB 130 and Vssm 160, thereby pulling the RBLB 130 voltage below the precharge logic high voltage. When a bit value stored at the first node T 152 is a logic low or when the word line WL 104 is de-asserted to a logic low, at least one of the read access transistor 110 and the read pull-down transistor 120 is open, thereby electrically cutting off the conductive path between RBLB 130 and VSSM 160. This results in substantially retaining the voltage at RBLB 130, which is equal to the precharge logic high voltage (assuming negligible leakage current).
However, supply voltage improvements such as increasing supply voltage from a ground reference (not shown) Vss=0 volts to Vssm 160=0.3 volts (for providing increased forward bias) or increasing WL 104 from 1.1 volts to 1.4 volts, which may have been made to improve writability to the 8T memory cell or to reduce power consumption, often cause level shift problems (e.g., between periphery and the memory cell array) during sensing of voltage at RBLB 130. In addition, a low level voltage (e.g., Vssm=0.3 volts) at RBLB 130 is comparable to a threshold voltage (Vt) of a transistor and may not be easily differentiated from a high logic level across corners of an array or other reduced power voltages during the sensing operation. As a result, the performance of the traditional 8T memory cell may be reduced and may result in increased read errors.